Self-planarizing low-temperature doped-silicate-glass...

Details Self-planarizing low-temperature doped-silicate-glass... Self-planarizing low-temperature doped-silicate-glass...

1998-11-20

2001-07-31

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S434000

Reexamination Certificate

active

06268297

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods.
BACKGROUND
Increased surface density and more surface layers made possible the advancement of circuits to VLSI densities, and more recently, ULSI levels. Due to shrinking gate lengths and inter-poly spaces, there has arisen a need for a phosphorous-doped oxide deposition process capable of filling the less than 0.5 micron gaps between polysilicon lines. Requirements for pre-metal dielectric (“PMD”) layers have to be reviewed as devices shrink even further, below the 0.25 micron generation, due to limited depth-of-focus, planarity, low thermal budget, and gap-fill of such small dimensions.
Moreover, with regard to transistor fabrication, since the distances between the source and drain are smaller and the junctions are shallower, there is also a second requirement of a low thermal budget after the transistors have been built. The doped dielectric layer used to isolate transistors from the overlying interconnect module are critical for electrical insulation as well as for gettering contamination which may change device characteristics. With shrinking inter-poly spaces, a void-free gap-fill pre-metal dielectric process is more important since any voids could open up during contact etch and cause metal filaments, as shown in FIG.
4
.
A low temperature pre-metal dielectric is essential due to the requirements for a low thermal budget process after transistor formation. Problems with the standard plasma CVD-PSG (chemical-vapor deposition - phosphosilicate glass) process have been, 1) gap-filling, 2) film stability, and 3) planarization.
A low temperature PMD process, in particular, is imperative to maintain low silicide sheet resistances, shallow junctions, low contact resistances, low fixed-charge density (high Cinv/Cox), high drive currents, and reduce dopant de-activation. Conventional techniques, such as reflowed boro-phosphosilicate glass (“BPSG”) and plasma enhanced PSG (“PEPSG”), used thus far, fail to meet these criteria.
High-Density Plasma
Integrated circuit processing with high-density-plasma (“HDP”) is currently a very active area of research. The key difference between HDP conditions and the plasma conditions formerly used in integrated circuit processing is the ionization percentage: under HDP conditions the ratio of ions to neutral species near the surface of the wafer (outside the dark space) will typically be 10 percent or more, as compared to a much smaller ionization percentage in conventional plasma reactors. This higher ionization fraction is typically achieved by using an RF power input for ionization which is not applied directly to the wafer surface. In addition, a second RF power input is applied to the wafer surface (through the conductive susceptor which holds the wafer), to apply a voltage to ion bombardment. (Note that the gas pressure under HDP conditions is not necessarily higher than in conventional plasma processing; indeed gas pressure under HDP conditions is often less than 100 milliTorr, since low pressures produce a longer mean free path and reduce recombination.)
Innovative Structures and Methods
The present application discloses a process using a high-density-plasma (“HDP”) environment such that a phosphorous-doped oxide, preferably with less than 4 percent (wt) can be deposited at less than 350 degrees C. The gap-fill is superior, self-planarization is evident, and film stability is good. This process is capable of filling the 0.4 micron spaces between the polysilicon gates or narrow lines without leaving any voids.
The disclosed low-temperature (less than 400 degrees C.) pre-metal dielectric scheme is shown to have a significant impact on simplifying process-integration and improving device yield. Moreover, this plasma CVD technique also has better native planarity, which reduces as-deposited topography and therefore the CMP polish time. The superior planarity of this PMD process reduces electrical defects at metallization and therefore improves the yield of good electrical die; it also eliminates the need for boron doping of the PMD layer and a high temperature anneal for reflow. The self-planarizing nature of the process reduces the amount of CMP polish time, which in turn reduces the cost of manufacture of the PMD level. Device and contact characteristics are shown to be superior to high-temperature PMD processes. This HDP process is found to have acceptable plasma damage performance comparable to parallel-plate plasma processes. Analysis of SRAM devices indicate that the yield for this low temperature PMD process was well over twice that for the conventional plasma enhanced PSG scheme. A further advantage is that high concentrations of phosphorous are avoided, which has the ability to create phosphoric acid with the introduction of moisture. Low temperature PMD is required for reduced contact and poly sheet resistance and improved Cinv/Cox. Gap-fill and planarity requirements are also stringent at sub-0.25 micron. The HDP-PSG scheme is shown to be electrically superior as well as simplifying process integration. Another advantage is this low-temperature PMD process is applicable to devices with 0.18 micron nodes.


REFERENCES:
patent: 5621241 (1997-04-01), Jain
patent: 5937322 (1999-08-01), Orczyk et al.
patent: 6030881 (2000-02-01), Papasouliotis et al.
S. Wolf and R.N. Tauber., Silicon Processing, Lattice Press, vol. 1, pp 188, 1986.

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