Method for forming a dummy active pattern

Details Method for forming a dummy active pattern Method for forming a dummy active pattern

1998-12-15

2001-05-15

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S129000, C438S223000

Reexamination Certificate

active

06232161

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a mask pattern for manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a dummy active mask pattern, by which the active regions can be protected from ion implantation.
2. Description of Related Art
Shallow trench isolation (STI), is widely used in manufacturing an integrated circuit. Forming STI includes the steps of forming a trench on the substrate by the anisotropic dry etching and filling the trench with oxide to provide a device insulation area. Therefore, in the process of forming a complementary metal-oxide semiconductor (CMOS) with sub-micron dimensions, STI is a better and scaleable insulation structure, and can prevent a “bird's beak” encroachment in local oxidation. In a conventional method of forming STI, a dummy active pattern is usually formed to prevent a “dishing effect” from occurring on larger STI areas in the process of chemical mechanical polishing (CMP). However, the presence of the dummy active pattern still affects the performance of the semi-conductor devices.
FIGS. 1A
to
1
C show cross-sectional views of a conventional method in which a dummy active pattern is used to form the STI. As shown in
FIG. 1A
, after defining a photo-resist layer with a dummy active pattern (not shown in
FIG. 1A
) on a substrate
100
, a plurality of dummy active areas
106
and shallow trenches
108
are formed thereon, and then an insulation layer
110
is deposited on the substrate
100
, and the shallow trenches
108
are filled.
Then, as shown in
FIG. 1B
, the insulation layer
110
is polished by CMP until it is level with the substrate
100
, whereby the shallow trenches
108
a
are formed. Then, a mask pattern (not shown in
FIG. 1B
) is used in for implanting ions into the substrate
100
to form an N-well
102
and a P-well
104
. Then, as shown in
FIG. 1C
, a dielectric layer
112
is formed on the substrate
100
and a metal layer
114
is sequentially deposited for forming plugs.
In light of the foregoing, although the conventional method of using dummy active areas on the substrate provides a method of preventing the dishing effect while performing CMP on the shallow trench isolation areas, the existence of dummy active areas make the trench isolation so narrow that a parasitic capacitance is formed between metal interconnections and dummy active areas after doping with N-type ions or P-type ions. This is due to the ions being implanted into the dummy active areas. Therefore there is a need to provide a method to prevent parasitic capacitance due to the interaction between dummy active areas and the metal line.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for forming a mask pattern to prevent ions from being doped into the dummy active areas while forming a P-well or an N-well. Hence the dummy active mask pattern formed by the present invention can prevent ions from being implanted into dummy active areas after the dummy active areas are formed. This will increase the resistivity of the dummy active areas, decrease parasitic capacitance while the current is applied, and decrease the RC delay.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, this invention provides a method of forming a dummy active pattern. First, a first pattern defining an N-well and P-well boundary and active areas, which are formed and distributed on the P-well and N-well, is provided on a mask. Then, a second pattern with a plurality of dummy active areas outside the areas of active areas are formed on the mask, wherein parts of the dummy active areas are distributed on the P-well and the other are on the N-well. Then, the first pattern is removed and the second pattern is reserved, wherein the second pattern is subsequently enlarged. Then, a third pattern that defines the P-well boundary and the N-well boundary is provided, wherein the P-well boundary of the third mask pattern and that of the first pattern are the same in size, but the N-well boundary on the third mask is shielded. The third pattern is used to expose the P-well boundary desired in the subsequent ion implantation process to allow the P-type ions being implanted to form the P-well. The enlarged second mask pattern overlaps with the third pattern which shielding the N-well and therefore, only the P-well of the substrate is implanted ions.
For the same reason, we provide a fourth pattern defining the N-well boundary and the P-well boundary, wherein the size of the N-well boundary is the same as that of the first pattern. However, the fourth pattern shields the P-well boundary and exposes the N-well boundary to let the N-type ions form the desired N-well in the subsequent ion implantation process. Then the fourth pattern composed with the enlarged second pattern. Thus the second composed pattern have similar functions with the first composed pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5885856 (1999-03-01), Gillbert et al.
patent: 5902752 (1999-05-01), Sun et al.
patent: 6020616 (2000-02-01), Bothra et al.

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