Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-08
2001-03-27
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S183000, C438S286000, C438S299000, C438S164000
Reexamination Certificate
active
06207511
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor devices and processes and more specifically to transistors having a gate on more than one side of the channel.
BACKGROUND OF THE INVENTION
As semiconductor devices continue to shrink into the submicron range, it becomes more and more difficult to maintain device performance. For example, in a MOSFET, current flows along the surface between the gate insulator and the silicon channel. The bulk of the channel does not contribute to the MOSFET current for gate voltage values well above the threshold voltage. As MOSFETS shrink, the surface area available for current flow naturally also shrinks.
One prior art structure that has been developed to increase MOSFET conduction is a double gate SOI design. A double-gate MOSFET
10
is shown in FIG.
1
. The lightly doped conducting channel
12
has a gate
14
on top of the channel
12
and a gate
16
on the bottom of the channel. In the fully depleted mode of operation, the channel is thin and lightly doped so that the combination of the two gate voltages completely depletes the silicon channel
12
from top to bottom. Although most of the current flows near the top and bottom surfaces of the channel
12
, inversion charge also flows in the volume of the thin fully-depleted channel for the case just above threshold voltage. The channel may be several tens of nanometers thick for a fully depleted double gate SOI transistor. One of the most significant fabrication problems occurs in aligning the top gate pattern to the bottom gate.
FIG. 2
shows a cross-section of a double gate MOSFET from source
20
to drain
22
showing the current flow.
FIG. 3
shows a different cross-section across the channel
12
looking from the drain
22
.
FIG. 4
is the same view as
FIG. 2
but with the top gate mis-aligned with respect to the bottom gate.
Another prior art structure is the “Gate all-around” MOSFET
30
shown in FIG.
5
. In MOSFET
30
, the channel
32
is surrounded by gate
33
. Gate
33
consists of a top gate portion
34
and a bottom gate portion
36
as in the double gate MOSFET, but also includes a gate portion
38
on the vertical edges on the channel
32
. The bottom
36
and top
34
gates are joined by etching a cavity in the buried oxide
39
below the channel silicon and then (after growing the gate oxide) depositing LPCVD polysilicon gate material into the cavity and over the channel
32
in one step.
Another prior art structure is the vertical SOI Delta structure
40
as shown in FIG.
6
. The vertically oriented channel
42
is built over bulk silicon by forming the silicon strip
48
covered on top and sides by nitride and then this strip
48
is separated from the silicon substrate by a LOCOS oxidation
44
that extends below the silicon strip
48
. A gate
46
is then formed over the channel
42
. Unfortunately, this structure does not permit a large area channel, source, or drain because such a larger area would prevent the LOCOS oxide
44
from completely separating the top silicon from the substrate
50
. Larger area source and drain are needed for placement of contacts and for probing pads.
Another prior art technique is an etched groove silicon permeable base transistor, shown in FIG.
7
. It has the component parts of a MESFET. A MESFET differs from a MOSFET by not having a gate insulator, having a gate material that forms a Schottky barrier diode with the channel, and having a channel, source, and drain of the same conductivity type. The device of
FIG. 7
is however a unipolar device with current flowing vertically down the volume of silicon strips and sharing a common drain with the substrate.
SUMMARY OF THE INVENTION
The invention described herein is a transistor having at least one strip channel in which the current flow is in the lateral direction between source and drain. The gate is located on the vertical sides and, if desired, the top of the strip channel. In a preferred embodiment of the invention, a disposable gate process is used that allows the source and drain regions to be self-aligned to the gate.
An advantage of the invention is providing a transistor in which increases the surface area between the gate or gate insulator and channel thus increasing conduction by allowing the inversion current to flow laterally along vertical surfaces between source and drain.
Another advantage of the invention is providing a transistor that has reduced short channel drain induced barrier lowering.
Another advantage of the invention is providing a transistor that has uniform gate overlap of source and drain.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings and claims.
REFERENCES:
patent: 3926694 (1975-12-01), Cauge et al.
patent: 4001048 (1977-01-01), Melling et al.
patent: 4996574 (1991-02-01), Shirasaki
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5757038 (1998-05-01), Tiwari et al.
Chapman Richard A.
Houston Theodore W.
Joyner Keith A.
Brady III W. James
Chaudhuri Olik
Doan Theresa
Garner Jacqueline J.
Telecky , Jr. Frederick J.
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