Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-17
2001-07-10
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S596000
Reexamination Certificate
active
06258682
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor process, and more particularly to a method of fabricating ultra shallow junction MOSFET.
BACKGROUND OF THE INVENTION
With the advent of the integrated circuit industry, the demand for device density increased becomes a trend. It is essentially to have extra-high density devices in a chip so as to achieve powerful commercial competitiveness. However, as a device scaled from one micron down to submicron or beyond, it may suffer more stringent problems. For examples, hot carriers effect and punchthrough effects are two of the major constraints in CMOS transistor scaling. Further, parasitic resistance and capacitance in the scaled device structure are required to avoid.
Other limiting factor for devices with submicron dimensions is the conductivity of the source/drain regions and the poly-gate. For example, the sheet resistance of diffusion regions increases from 25 &OHgr;/sq - in a 1 &mgr;m technology to 50 &OHgr;/sq - in a 0.5 Am technology. A self-aligned silicide technology, namely salicide, involving the formation of silicide on poly-gate, source and drain contact simultaneously. The salicide process can provide not only low-sheet resistance for S/D regions and for gate electrode in MOS devices but also a very clean suicide-silicon interface. Further, it does not require any additional lithography and etching. In addition, the alignment was predetermined.
However, the salicide process requires consuming a portion of silicon substrate while the silicide forming metal reacts with the semiconductor substrate. The silicidation process will countervail the ultra shallow junction formed for scale down devices. Hence, it is desired to have a silicon layer deposit on the source/drain regions for silicidation. To ensure the source/drain region isolate from gate region during CVD deposit silicon layer process, an oxide layer is usually formed before the layer deposited. The processes thus require complex process.
Thus an object of the present invention is to simplify the fabrication process.
SUMMARY OF THE INVENTION
The present invention discloses a method of fabricating ultrashallow junction MOSFET. The method comprises following steps. First of all, a semiconductor substrate having gate region and source/drain regions defined are prepared. An IMP process is then performed to anisotropic deposit silicon layer on the top surfaces of the gate region, source/drain regions. No silicon layer is formed on the sidewall of the gate region. A LDD ion implant into IMP silicon layer is then performed. A thermal oxidation process is then performed to partially oxidize a portion of IMP silicon layer and the sidewall polysilicon of the polygate region to ensure the polygate region is isolated from the source/drain regions. Furthermore, the impurities will be driven into semiconductor substrate to form ultra-shallow junction. After that, a CVD insulating layer is formed on all areas. An anisotropic etching is then performed to form sidewall spacers and expose the remnant IMP silicon layer on both source/drain regions and gate region. Thereafter, a heavily doped ion implantation through IMP silicon layer into semiconductor substrate is carried out. A refractory metal is then deposited on entire regions. After that, a first RTP step is performed to form silicide layer on the source/drain regions and on the gate region. Subsequently, the unreacted metal layer is removed. Another RTP step is then performed again to stabilize the silicide layer, activate the conductive impurities, and form deep junction.
REFERENCES:
patent: 5858849 (1999-01-01), Chen
patent: 5966607 (1999-10-01), Chee et al.
patent: 6100191 (2000-08-01), Lin et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Chaudhari Chandra
Vanguard International Semiconductor Corporation
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