Method of pocket implant modeling for a CMOS process

Details Method of pocket implant modeling for a CMOS process Method of pocket implant modeling for a CMOS process

1998-12-18

2001-08-14

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S014000, C438S017000, C438S306000, C438S307000

Reexamination Certificate

active

06274449

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing and more particularly to a method of pocket implant modeling for a CMOS process.
BACKGROUND OF THE INVENTION
The density of microelectronic devices on a semiconductor substrate may be increased by decreasing the size or line width of the microelectronic devices. The decrease in line width allows a large number of microelectronic devices to be formed on a semiconductor substrate. As a result, the competing power and speed of semiconductor component may be greatly improved.
In order to decrease the line width of a microelectronic device, the lateral dimensions of conductor, semiconductor and insulator regions forming each microelectronic device must be reduced. One such region much focused on is the formation of a gate in a CMOS transistor. The gate length of a microelectronic device is one of the most critical areas to address if an increase in the density of microelectronic devices is to be successfully achieved.
One problem associated with decreasing the gate length of CMOS transistors is the ability to create an adequate source and drain region of that transistor by subsequent processing steps as gate lengths continue to shrink. Ideally, the conductive regions comprising a source and drain of a transistor should slightly overlap under a gate body to create a transistor with optimal operating characteristics. CMOS transistors exhibiting optimal overlap can achieve the highest drive current and optimal threshold voltages. Overlap occurs because of the diffusion of dopant ions during and after the formation of the conductive source and drain regions.
As dopant ions are implanted into the surface of a substrate the dopant ions decay or diffuse laterally. Because dopant implantations are traditionally aligned at the edges of a gate body, any lateral diffusion in the direction of the gate creates a region of overlap. The shorter the gate length of the microelectronic device, the more detrimental an unoptimized overlap may be to the performance of the microelectronic device. For example, a minimal overlap compared to the total gate length in a 0.5 micron device becomes significant in a sub 0.25 micron device.
One means of optimizing dopant overlap under the gate body is through the creation of a pocket implant region that is doped utilizing a dopant species that counteracts the dopant species used to create the source and drain regions. The primary purpose of pocket implants is to achieve graded doping in the channel region of a device. This graded doping reduces the short channel effects of the device and reduces drive current sensitivity to changes in gate length, thereby improving device performance. The pocket implant is ideally situated just under the gate edge in the same vertical dimension as the overlap that is to be optimized. The dopant used to create the source and drain regions has a concentration gradient such that the concentration of the implant outside the gate is very high and begins to drop exponentially at the gate edge. The pocket implant is designed to counteract to some degree the small dopant concentration that exists inside the gate edges. Pocket implants have been successfully utilized to obtain high drive currents and otherwise desirable performance characteristics in microelectronic devices by optimizing source and drain dopant overlap. Even in smaller device geometries, such as devices using sub 0.25 micron gate lengths, pocket implants have been successfully utilized.
However, no systematic means currently exists for determining which optimal conditions during pocket dopant implantation best optimize source and drain dopant overlap. Currently, for each newly manufactured semiconductor device, with its own specific doping characteristics, device geometries, and operating conditions, a wide range of implant dosages, energies, and angles of implantation must be attempted to create a pocket implant that successfully optimizes source and drain region gate overlap.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a method of pocket implant modeling for a CMOS process that allows a systematic means of selecting the appropriate conditions under which to create an effective pocket implant.
In accordance with the teachings of the present invention, a method of determining the thermal straggle of microelectronic devices having a pocket dopant implant that is formed under substantially the same doping conditions is disclosed that comprises measuring the operating characteristics of each device and obtaining a one-dimensional doping profile of dopant ions in the devices. A total lateral straggle of the dopant ions in the devices is determined in response to the operating characteristics and the one-dimensional doping profile of the dopant ions. An as-implanted straggle of the dopant ions in the devices is determined in response to the doping conditions. A thermal straggle of the dopant ions is calculated utilizing the as-implanted straggle and the total lateral straggle.
The disclosed invention provides several technical advantages. For example, the disclosed invention offers a previously unavailable, easily implemented, simple and effective means of modeling the pocket implant and device performance characteristics. The invention allows the prediction of device operating characteristics based on a particular pocket implant dosage, energy, and implantation angle. The invention also results in substantial savings in silicon wafers previously used to test the operating characteristics of microelectronic devices for different implant dosage conditions. An additional advantage of the invention is that it allows for the more cost effective use of pocket implants in small device geometries. Furthermore, the invention provides a systematic method that can be utilized across a broad spectrum of device technologies to determine the correct dopant implantation conditions to be followed for optimal device performance. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.


REFERENCES:
K. Vasanth, et al., “A Pocket Implant . . . CMOS Process Flows”, Dec. 05, 1996.*
1996 IEEE “An Efficient Method for Modeling the Effect of Implant Damage on NMOS Devices Using Effective Profiles and Device Simulation,” pp. IEDM 96-717 thru IEDM 96-720 (K. Vasanth, S. Saxena, V. McNeil, S. List, J. Davis and D. Kapila).

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