Method of forming a MOS transistor

Details Method of forming a MOS transistor Method of forming a MOS transistor

1999-12-09

2001-05-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000

Reexamination Certificate

active

06238988

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of forming a MOS transistor on a semiconductor wafer.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) is a very common electrical device in integrated circuits. A gate, a source, and a drain together comprise the MOS transistor to form a unit with four nodes. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digital solid switch. With the increasing sophistication of production technology, the size of these units has become smaller and smaller, and consequently so, too, has their channel length. However, when the channel length is too short, a short channel effect can occur that affects the switching function of the gate.
A lightly doped drain implantation process is currently employed to resolve the short channel effect. Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are cross-sectional diagrams of the prior art method of forming a MOS transistor. As shown in
FIG. 1
, the MOS transistor is formed on a semiconductor wafer
10
. The semiconductor wafer
10
comprises a silicon substrate
12
, and a dielectric layer
14
installed on the silicon substrate
12
.
As shown in
FIG. 2
, during the formation of the MOS transistor, a gate
16
is formed on a predetermined region of the dielectric layer
14
. The dielectric layer
14
beyond the predetermined region is removed down to the silicon substrate
12
. As shown in
FIG. 3
, a first ion implantation process
18
is performed to form two doped regions on the silicon substrate
12
adjacent to two opposite sides of the gate. Each doped region functions as a lightly doped drain (LDD)
22
of the MOS transistor.
As shown in
FIG. 4
, two spacers
24
made of insulating material are formed on opposite sides of the gate
16
. As shown in
FIG. 5
, a second ion implantation process is performed to form two doped regions on the silicon substrate
12
adjacent to the spacers
24
. The two doped regions function as a source
27
and a drain
28
of the MOS transistor.
Please refer to FIG.
6
.
FIG.6
is a cross-sectional diagram of the MOS transistor after a self-alignment silicide process has been performed. The self-alignment silicide (salicide) process is performed to reduce the contact resistance of each silicon surface. As shown in
FIG. 6
, after the self-alignment silicide process, a silicide layer
32
is formed on the surface of the gate
16
, the source
27
and the drain
28
of the MOS transistor.
The length of the spacer
24
on two opposite sides of the gate
16
decides the final length of the LDD
22
. In order to keep the junction deep between the source
27
and the drain
28
, the width of the spacer
24
is always about 800~1500 Å. This prevents the device driving current of the unit from being affected by thermal treatment processes or the source and drain implantation process, and also avoids device shorting effects. However, with the reduction of the unit size, the LDD
22
also becomes smaller and thinner. This lower implantation energy of the LDD greatly increases the extension external resistance of the LDD
22
, and decreases the extension coupling between the gate and the LDD
22
.
SUMMARY OF THE INVENTION
It is therefore a primary objective to the present invention to provide a method of forming a MOS transistor on a semiconductor to solve the above mentioned problems.
In a preferred embodiment, the present invention relates to a method of forming a metal oxide semiconductor (MOS) transistor on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, the method comprising:
forming a gate having a rectangular-shaped cross-section on a predetermined region of the silicon substrate;
performing a first ion implantation to form two doped regions on the silicon substrate adjacent to two opposite sides of the gate, each doped region functioning as a lightly doped drain of the MOS transistor;
forming a first spacer with insulating material on each of the opposite sides of the gate;
forming a uniform conductive layer on the semiconductor wafer, the conductive layer covering the silicon substrate, the gate and the two first spacers;
forming a uniform sacrificial layer on the conductive layer;
performing a first etching process to remove a portion of the sacrificial layer, the remaining sacrificial layer on the conductive layer forming two second spacers outside of the first two spacers;
performing a second etching process to remove the conductive layer on the silicon substrate and on the top of the gate, the second spacers being used as a mask so that the conductive layer covered by the second spacers will not be removed thereby forming two remaining conductive layers, the first spacers isolating the two remaining conductive layers from the gate;
removing the second spacer completely;
performing a second ion implantation to form two doped regions just under the silicon substrate adjacent to each of the two remaining conductive layers, the two doped regions functioning as a source and a drain of the MOS transistor.
It is an advantage of the present invention that the resistance of the LDD will be reduced, increasing the device driving current of the MOS transistor and improving its electrical performance.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5091763 (1992-02-01), Sanchez
patent: 5766969 (1998-06-01), Fulford, Jr. et al.
patent: 5847428 (1998-12-01), Fulford, Jr. et al.

Affiliated with

Also associated with

Rating

Method of forming a MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a MOS transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2440594