Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365205, G11C 1300, G11C 1140

Patent

active

050181050

ABSTRACT:
A semiconductor memory device includes a pair of bit lines and a sense amplifier device. Each of the pair of bit lines has a parasitic capacitor and a memory cell connected thereto respectively. The memory cell has an electric capacity and a word line connected to a gate of a transistor. The sense amplifier device has a first sense amplifier, a second sense amplifier, a first transistor, a second transisitor and a third transistor for amplifying a potential difference caused by a balance between the parasitic capacitor of one bit line and the electric capacity of one memory cell connected to the one bit line after the pair of bit lines are precharged and the word line of the one memory cell is raised.

REFERENCES:
patent: 4953129 (1990-08-01), Kobayashi et al.

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