Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-01-12
2001-09-18
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S750000, C257S751000, C257S752000
Reexamination Certificate
active
06291891
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device of multi-level wiring structure such as a logic LSI (Logical Large Scale Integrated Circuit), a DRAM (Dynamic Random Access Memory), SRAM (Static RAM), a CMOS (Complementary Metal Oxide Semiconductor) or a bipolar transistor (Bipolar Transistor), especially, to a formation of multi-level wiring which includes via-contact formation using wiring formation and a conductive pillar-shaped structure (pillar), and a semiconductor device which has a multi-level wiring structure.
Conventionally, in general, when a connection plug, which electrically connects between the wirings of the upper level and the lower level in the multi-level wiring structure of the semiconductor device, is formed, a method of opening a contact hole by using a reactive ion etching (RIE (Reactive Ion Etching)) method etc. for an interlevel insulation film, and forming the connection plug by burying a conductive material such as metal is used.
This conventional art has the following disadvantages. At the RIE for the opening of the contact hole, physical damage and corrosion are caused on the surface of lower level wiring exposed to the bottom of the contact hole with the etching gas and the sputtered particle. A contact resistance between the above-mentioned connection plug and the lower level wiring rises by adhering the etching residue and the sputtered particle. When the contact hole is not formed at a desired position by the occurrence of the missalignment with the lower wiring pattern at formation of the contact hole, the lower wiring side and the interlevel insulation film thereunder are excessively etched by RIE. In addition, the undesirable short-circuit with the wiring of the lower level is occurs, and the cave remains around a fine wiring. As a result, the reliability lowers.
When the lower level wiring is formed, a method of forming a conductive pillar-shaped structure (pillar) and the lower level wiring at the same time is known. This method is a method of depositing a metal film on the insulation film formed on the semiconductor substrate, forming the connection plug with a photo-lithography and the etching methods such as an RIE and leaving a metal film in the trench to form the lower level wiring. However, the lower level wiring is the same material as the connection plug, and changing both of the material cannot broaden the variety of the selection of the material. Moreover, when the connection plug is etched, the lower level wiring might be over-etched. In addition, the missalignment might be occurred when the connection plug and the upper level wiring are connected.
Recently a high speed operation has come to be requested to the device. Therefore, a lower resistance material is required as for the wiring material. Copper (Cu) has been paid attention so as to respond to the request and is multi-used. The electrical resistivity of the copper is 1.8 &mgr;&OHgr;cm, and it is greatly low among the wiring material. Besides this, tungsten (W) whose resistivity is 10 to 20 &mgr;&OHgr;cm and aluminum (Al) whose resistivity is 3 to 4 &mgr;&OHgr;cm are used well as a wiring material. Therefore, AlCu alloy is used as any of the lower level wiring
12
, the connection plug
14
(conductor pillar), and the upper level wiring
18
shown in FIG.
1
A and
FIG. 1B
, for example, but is considered that the wiring resistance is reduced by using Cu for the lower level wiring
12
and the upper level
18
, and using Al for the connection plug
14
.
However, the.inconvenience might happen when Cu is used as it is. First, Cu has characteristics to diffuse into the insulation film in the state of the atom when Cu is covered by the insulation film. Especially, the moving of Cu becomes active if Cu is heated by the use of the device and the heat-treating step under manufacturing, then the wiring is destroyed and comes to cause the disconnection and the short-circuit accident easily. Moreover, the surface is oxidized when Cu is exposed in (the) air, and advantage of the low resistance is lost.
Moreover, in the above-mentioned pillar technology, since the pillar-shaped structure (pillar) is formed only to connection part of the lower level wiring and the upper level wiring, the ratio of the region where the pillar-shaped structure is formed becomes very small and is about several % or less of the whole. Therefore, the pillar-shaped structure is excessively etched, for example, when the drying etching, and the processing of the pillar-shaped structure becomes difficult. The planarity of the interlevel insulation film formed after processing of the pillar-shaped structure deteriorates.
As described above, since the ratio of the region where the pillar-shaped structure is formed is very small when the pillar technology is used for the connection of the lower level wiring and the upper level wiring, there is a subject matter of a bad processing control of the pillar-shaped structure and a bad planarity of the interlevel insulation film.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is as follows.
(1) To provide a semiconductor device manufacturing method having the multi-level wiring structure which can secure the space, in which the contact structure between the lower level wiring and the upper level wiring is arranged, before depositing the interlevel insulation film, can prevent from the damage at RIE and impurities on the surface of wiring under the contact hole, and can secure the reliability with the contact of the lower level wiring even if the missalignment is occurred at the contact hole.
(2) To provide a semiconductor device manufacturing method which has the multi-level wiring structure to connect between wirings in which the protection film to control the diffusion of the wiring material into the insulation film (or, to control the oxidation of the wiring material) can be deposited without greatly increasing steps, and the semiconductor device manufactured by the method.
(3) To provide a manufacturing method capable of improving the processing controllability and the planarity of the interlevel insulation film of the pillar-shaped structure (pillar) when the pillar technology is used to connection step of the lower level wiring and the upper level wiring.
According to the first aspect of the present invention, in the semiconductor device manufacturing method or the semiconductor device, a hard mask is formed on upper portion of the pillar, the process is advanced with leaving the hard mask, and the hard mask is removed immediately before connecting the pillar with the upper level wiring, when the lower level wiring (the first buried wiring) and the upper level wiring (the second wiring) are connected with the pillar-shaped structure (pillar). Where, it is desirable to form a protection film on the surface of the lower level wiring uncovered with at least the pillar-shaped structure after the pillar-shaped structure is formed.
The hard mask may be a silicon oxide, a silicon nitride, or a tungsten.
The first aspect of the present invention comprises the following features. First, after the first buried wiring (lower level wiring) which consists of Cu is formed on the first interlevel insulation film, a conductive layer, in which the connection plug which consists of, for example, Al/W/WN or Cu, etc. is formed, is formed. Next, this conductive layer is processed to the connection plug by the lithography technology and the RIE method. That is, in the first aspect of the present invention, a hard mask materials such as the silicon nitride film or the silicon oxide film for forming the connection plug is deposited as an etching mask on a conductive layer where the connection plug is formed. The protection film such as silicon nitride films (Si
3
N
4
) with an effect by which the diffusion of Cu to the interlevel insulation film is controlled and an effect by which the oxidation of the Cu surface is controlled is deposited on the connection plug and the first interlevel insulation film by the CVD method or the reactiv
Anand Minakshisundaran Balasubramanian
Higashi Kazuyuki
Iijima Tadashi
Kajita Akihiro
Kaneko Hisashi
Clark Jhihan B
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Semiconductor device manufacturing method and semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device manufacturing method and semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device manufacturing method and semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2438005