Method of making dense SOI flash memory array structure

Details Method of making dense SOI flash memory array structure Method of making dense SOI flash memory array structure

1999-10-07

2001-07-03

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S155000, C438S164000, C438S588000

Reexamination Certificate

active

06255171

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improved semiconductor structure for high density device arrays, such as flash memory arrays. In particular, this invention relates to a Silicon-On-Insulator (SOI) flash memory array of fully isolated device islands that can be implemented with a small feature size, and a process for its formation.
BACKGROUND OF THE INVENTION
SOI technology provides many advantages when used in Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs). One primary advantage is a significant reduction of parasitic capacitance between a source/drain and a substrate. Other major advantages include elimination of latch-up, reduction of chip size and/or increased device density, and increased circuit speed. SOI devices also have lower power requirements and higher speeds compared to non-SOI devices, making SOI technology popular for use in battery-operated equipment.
The advantages of SOI structures result from the total isolation of the device islands from the substrate. Total isolation has been achieved using a sapphire substrate instead of a semiconductor substrate, but the resultant product is expensive and the quality of the crystalline silicon grown on sapphire is usually poor. Processes to achieve device-substrate isolation using a silicon substrate are known, but such processes may not achieve total isolation, and may cause defects in the resultant structures.
SOI structures may be formed through a variety of processes, including SIMOX, wafer bonding, FIPOS and etch and oxidation processes. Separation by Implanted Oxygen (SIMOX) involves oxygen ion implantation into a silicon substrate to form a buried oxide insulating layer. This method is expensive and has the disadvantage of damaging the crystalline structure of the silicon above the insulating layer due to the passage of high energy oxygen ions.
Wafer bonding is another technique for forming an isolation layer in a substrate. It involves the fusing together of two oxidized silicon wafers in a high-temperature furnace. However, wafer bonding is an undesirable technique because it increases the substrate thickness, and has low production yields due to voids and particles interfering with adequate bonding between the wafers.
The Full Isolation by Porous Oxidized Silicon (FIPOS) process forms an insulating layer through the initial formation of a doped layer in the silicon substrate, covered with a layer of undoped epitaxial silicon. The substrate is then anodized to create a porous layer of silicon under islands of undoped silicon in the substrate. The FIPOS process is slow and expensive, and produces a substrate with a tendency to warp or curl due to the thermal stresses it has undergone.
Another known technique used to form an isolation layer is a series of etch and oxidation steps used to create silicon islands, as described in U.S. Pat. No. 4,604,162. Islands are formed by the etching and subsequent partial undercutting of the islands. Silicon filaments maintain the connection of the islands to the substrate during the undercutting step, and the subsequent thermal oxidation step. During thermal oxidation, which creates an isolation layer under the islands, expansion of the oxide subjects the islands to substantial mechanical stress and crystal damage. The silicon filaments connecting the islands to the substrate are also under tensile stress that creates dislocations of the islands, resulting in high junction leakage and low carrier mobility.
In addition to the isolation of the devices from the substrate, it is also important to isolate the devices from each other. The use of silicon device islands with isolation trenches is known, but such devices typically do not have a high functional density. As the minimum feature size decreases, the number of devices in a chip area (active device density) increases, but the area occupied by interconnection lines on the chip surface minimizes the number of interconnected devices in a chip area (functional density). To be effective, a high density device array should maximize both active device density and functional density.
Nonvolatile semiconductor memory devices based on Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are well-known in the art. There are currently three types of MOSFET nonvolatile memory devices in use: EPROMs, EEPROMs, and Flash EEPROMs. A Flash EEPROM is comprised of an array of non-volatile storage cells from which data may be read any number of times without disturbing the state of the stored data. Each cell is an individual Field Effect Transistor (FET) that stores a bit of information as the presence or absence of an electrical charge on a floating gate.
Data is written to a cell by hot electron injection which occurs when a high positive voltage is applied to both the control gate and the drain line. Some of the electrons in the device channel will acquire sufficient energy to jump the energy barrier at the interface of the device channel and the tunneling oxide. Once they are in the tunneling oxide, the electrons are pulled toward the floating gate by the positive voltage on the control gate. This results in charge collection on the floating gate, which in turn affects the threshold voltage of the control gate.
The cells are read by addressing the control gate and drain line of a cell with a positive voltage (e.g., 3 to 5 volts). If the floating gate is negatively charged (logical state “1”), the threshold voltage will be high and the cell device will not turn on when addressed. If the floating gate is uncharged (logical state “0”), the threshold voltage will be low, and the device channel will invert when addressed, causing a resulting current in the drain line that can be sensed by current sensing methods known in the art.
Erasure is accomplished by Fowler-Nordheim tunneling, also called “cold electron” tunneling. Cold electron tunneling is a quantum-mechanical effect allowing electrons to pass through, instead of over, the energy barrier at the interface of the device channel and the tunneling oxide. Because the electrons are passing through the barrier, this process requires less energy than hot electron injection, and can occur at a lower current density. A high voltage (e.g. 10 volts) is applied between the control gate and the source, causing electrons to leave the floating gate and tunnel through the tunneling oxide to the drain. Any individual cell or all cells may be simultaneously erased by applying an electrical pulse to any or all cells.
Typically EEPROMs are comprised of an array of paired transistors: a select or access transistor and a storage transistor. Many flash EEPROMs combine these two transistors into one device—a split gate transistor with two gates sharing a single device channel. The control gate serves the function of the select or access transistor, and the floating gate serves as a storage device. The split gate configuration alleviates the over-erase problem caused by Fowler-Nordheim tunneling. Over-erase occurs because Fowler-Nordheim tunneling is not a self-limiting process, and the floating gate not only loses negative charge when erased, but becomes positively charged. The layered gate structure eliminates this over-erase problem, but results in a larger cell size.
The easy reprogrammability, inherent short access time and non-volatility of the stored data make flash memory very attractive for many computer applications. However, high density flash memory cells have been difficult to produce so far. Although densities as high as one cell per F
2
(lithographic feature square) are known, they are typically fabricated by processes that are not easily integratable with the technology needed to produce support circuits and other logic function devices, and the flash cell structure itself may not be integratable. Conventional memory cells which are directly compatible with existing VLSI technologies require an area of 8 F
2
or more.
There is a need for a high density fully isolated semiconductor structure suitable for use in flash memory arrays.
SUMMARY

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