Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-16
2001-07-31
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S623000, C438S633000, C438S634000
Reexamination Certificate
active
06268277
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is related to a method fabricating a semiconductor device with reduced intralayer capacitance between interconnect lines and a resulting semiconductor structure.
Intralayer (or intralevel) capacitance is a major obstacle in achieving higher levels of integration. Higher levels of integration require smaller distances between metal lines with the region between metal lines having correspondingly higher aspect ratios (i.e., the ratio between the gap height and gap width). With the continual improvement in reduction of metallic line widths to the submicron range, interconnect delays become an increasing problem because of parasitic capacitance between the interconnect lines.
Several techniques have been utilized to reduce the dielectric constant between spacings of metal lines. Some proposals utilize interposed inorganic spin-on materials having low dielectric constants as, for example, hydrogen silsesquioxane (HSQ) or fluorinated silicon dioxides. However, these methods are successful only in reducing the dielectric constant to approximately 3.0 and involve complicated and expensive processing steps. Moreover, the resulting dielectric constants are not as low as desired especially with the continual push for higher integration resulting in ever higher aspect ratios.
An alternative method is to utilize an air gap between neighboring metallic lines so as to achieve the dielectric constant of approximately one. A conventional method utilizing an air gap interposed between adjacent metal lines is shown in
FIGS. 1-4
. Reference is also made to prior U.S. Pat. No. 5,641,712 and the article by J. G. Fleming and E. Roherty-Osmun entitled “Use of Air Gap Structures to Lower Intralevel Capacitance,” Feb. 10-11, 1997 DUMIC Conference, both of which documents are incorporated herein by is reference.
FIG. 1
illustrates a portion of an interconnect structure
10
showing a silicon dioxide layer
12
, a metalized layer such as aluminum
14
, and a patterned photoresist layer
16
. The interconnect structure
10
is formed on a semiconductor chip which is part of a semiconductor wafer. The metal layer
14
is etched away to form metal lines
20
,
22
and
24
, after which the photoresist layer
16
is stripped away with the resulting structure shown in
FIG. 2. A
dielectric
28
(e.g., SiO2) is now deposited over the structure of
FIG. 2
in such a manner as to enclose air gaps
32
and
34
as shown in FIG.
3
. The manner of depositing the dielectric layer
28
is known in the art as shown in the aforementioned U.S. Pat. No. 5,641,712 and may include inert ion sputtering and may be done with or without the formation of spacers. After the dielectric layer
28
is deposited a second dielectric layer
38
(e.g., HSQ) is utilized over dielectric layer
28
. A second dielectric layer is typically planarized and the process may then be repeated.
While the above-described process is successful in entrapping air gaps between metal lines, the process may not be utilized to create air gaps when a damascene process is used for metalization.
SUMMARY OF THE INVENTION
The invention is directed to a method of creating air gaps or air voids between metal lines made using a damascene process. The resulting structure exhibits reduce parasitic (intralevel) capacitance and permits higher aspect ratio metalization layers to be used to achieve higher levels of integration.
The invention may be characterized as a method of reducing intralevel capacitance in a damascene metalization process using the steps of (a) forming a metalization pattern using a damascene process which includes forming at least first and second metal regions separated by a dielectric or electrically insulating region, (b) forming an air gap at least partially within the dielectric or electrically insulating region, and (c) sealing the air gap to entrap the air gap between the at least first and second metal regions thereby reducing intralevel capacitance between the at least first and second metal regions.
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patent: 5476817 (1995-12-01), Numata
patent: 5639688 (1997-06-01), Delgado et al.
patent: 5641712 (1997-06-01), Grivna et al.
patent: 5654240 (1997-08-01), Lee et al.
patent: 5666398 (1997-09-01), Havemann et al.
patent: 5783481 (1998-07-01), Brennan et al.
patent: 5814555 (1998-09-01), Bandyopadhyay et al.
patent: 5987372 (1999-04-01), Howard
Fleming et al., “Use of Air Gap Structures to Lower Intralevel Capacitance”, DUMIC Conference, Feb. 10-11, 1997, pp. 139-146.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Foley & Lardner
Rao Shrinivas H.
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