Random access memory with a serial register arranged for quick a

Details Random access memory with a serial register arranged for quick a Random access memory with a serial register arranged for quick a

1991-03-21

1994-05-10

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518912, 36523004, 365221, 365240, G11C 700

Patent

active

053114680

ABSTRACT:
A random access memory includes a memory array of storage cells arranged in addressable rows and columns. A serial register is coupled to the memory array and to a serial register address decoder. A serial counter generates and applies to the serial register address decoder a sequence of addresses starting with an initial tap address. In response to the initial tap address, a first data bit is read out of an addressed storage cell of the memory array and is applied to a first input of a multiplexer. The initial tap address either is passed to the serial register address decoder or is incremented and applied to the serial register addressed decoder for accessing a second data bit from the serial register to a multiplexer. The initial tap address is incremented before passage only if the least significant bit of the initial address is odd.

REFERENCES:
patent: 4281401 (1989-07-01), Redwine et al.
patent: 4639890 (1987-12-01), Heilveil et al.
patent: 4747081 (1988-05-01), Heilveil et al.

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