Method for fabricating CMOS field effect transistors having sub-

Details Method for fabricating CMOS field effect transistors having sub- Method for fabricating CMOS field effect transistors having sub-

Filed on

1995-04-04

Date issued

1997-07-08

Examiner

Prenty, Mark V.

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

257387, 257755, 437 41, H01L 2976, H01L 21265

Type

Patent

Status

active

Patent number

056464355

Description

ABSTRACT:
A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths and shallow source/drain junction depths was achieved. The method for fabricating the FET includes a conducting layer that is deposited and patterned over the source/drain areas of the FET. The sub-quarter micrometer channel length was achieved by reducing the channel opening formed in the conducting layer using sidewall spacer techniques. The conducting layer on the substrate and under the source/drain polysilicon layer also serves as an interface to the diffusing source/drain dopants, and shallow junctions are formed that are about 0.06 to 0.08 um depth. The conducting layer also serves as a low resistant ohmic contact to the source/drain areas.

REFERENCES:
patent: 4914500 (1990-04-01), Lin et al.
patent: 5071780 (1991-12-01), Tsai
patent: 5079617 (1992-01-01), Yoneda
patent: 5196357 (1993-03-01), Boardman et al.
patent: 5548143 (1996-08-01), Lee
"A Sub 0.1 um Grooved Bate MOSFET with High Immunity to Short-Channel Effects" by J. Tanaka et al, IEDM Proceedings, of the IEEE 1993, pp. 537-540, Dec. 1993.

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