Method of making CMOS output buffer with enhanced ESD resistance

Details Method of making CMOS output buffer with enhanced ESD resistance Method of making CMOS output buffer with enhanced ESD resistance

1996-04-23

1997-04-08

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438232, H01L 218238

Patent

active

056187408

ABSTRACT:
The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

REFERENCES:
patent: 4894694 (1990-01-01), Cham et al.
patent: 5262344 (1993-11-01), Mistry
patent: 5272097 (1993-12-01), Shiota
patent: 5416036 (1995-05-01), Hsue
patent: 5529941 (1996-06-01), Huang

Affiliated with

Also associated with

Rating

Method of making CMOS output buffer with enhanced ESD resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making CMOS output buffer with enhanced ESD resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making CMOS output buffer with enhanced ESD resistance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2397399