Maintenance registers with Boundary Scan interface

Details Maintenance registers with Boundary Scan interface Maintenance registers with Boundary Scan interface

1997-10-31

2000-04-18

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714 30, 714703, G01R 3128, H02H 305

Patent

active

060528087

ABSTRACT:
Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.

REFERENCES:
patent: 5404358 (1995-04-01), Russell
patent: 5448576 (1995-09-01), Russell
patent: 5574733 (1996-11-01), Kim
patent: 5610530 (1997-03-01), Whetsel
patent: 5621739 (1997-04-01), Sine et al.
patent: 5659552 (1997-08-01), Ke et al.
patent: 5774477 (1998-06-01), Ke

Affiliated with

Also associated with

Rating

Maintenance registers with Boundary Scan interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Maintenance registers with Boundary Scan interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Maintenance registers with Boundary Scan interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2345832