Method for making asymmetrical N-channel and symmetrical P-chann

Details Method for making asymmetrical N-channel and symmetrical P-chann Method for making asymmetrical N-channel and symmetrical P-chann

1996-09-03

2000-04-18

Fahmy, Wael M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438306, 438307, 438231, 438232, H01L 21336

Patent

active

06051471&

ABSTRACT:
An asymmetrical N-channel IGFET and a symmetrical P-channel IGFET are disclosed. The N-channel IGFET includes heavily doped and ultra-heavily doped source regions, and lightly doped and heavily doped drain regions. The P-channel IGFET includes lightly doped and heavily doped source and drain regions. Forming the N-channel IGFET includes forming a gate with first and second opposing sidewalls, applying a first ion implantation to implant lightly doped N-type source and drain regions, applying a second ion implantation to convert the lightly doped N-type source region into a heavily doped N-type source region without doping the lightly doped N-type drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped N-type source region outside the first spacer into an ultra-heavily doped N-type source region without doping a portion of the heavily doped N-type source region beneath the first spacer, and to convert a portion of the lightly doped N-type drain region outside the second spacer into a heavily doped N-type drain region without doping a portion of the lightly doped N-type drain region beneath the second spacer. Advantageously, both IGFETs reduce hot carrier effects, and the N-channel IGFET has particularly low source-drain series resistance.

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