Drain and source engineering for ESD-protection transistors

Details Drain and source engineering for ESD-protection transistors Drain and source engineering for ESD-protection transistors

1998-05-04

2000-04-18

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438286, 438919, H01L 218238

Patent

active

060514582

ABSTRACT:
A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N- LDS/LDD regions in the P-well. Form N- LDS/LDD regions in the P-well and P- lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N- LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P- LDS/LDD regions in the N-well in the source/drain sites.

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