Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1987-01-20
1989-05-16
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365203, 365205, 307290, G11C 700
Patent
active
048315907
ABSTRACT:
A semiconductor memory device in which an output data bus (14) is precharged at a middle potential level prior to reading out data. A Schmidt Trigger circuit (39) having a hysteresis loop in input-output characteristics is provided between the output data bus (14) and a data output buffer (15). This allows the data output buffer (15) to maintain a stable output (16) while precharging the data bus (14).
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U. Tietze et al, "Halbleiter-Schaltungstechnik", Springer-Verlag Berlin, 1976, pp. 476-506.
"A Fault-Tolerant 30 ns/375 mW 16K x 1 NMOS Static RAM", Kim C. Hardee et al, Journal of Solid-State Circuits, vol. SC-16, No.5, Oct. 1981, pp. 435-443.
Gossage Glenn A.
Hecker Stuart N.
Mitsubishi Denki & Kabushiki Kaisha
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