Method for manufacturing stacked dynamic random access memories

Details Method for manufacturing stacked dynamic random access memories Method for manufacturing stacked dynamic random access memories

1996-10-18

1998-01-06

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438381, H01L 218234

Patent

active

057054380

ABSTRACT:
A method for manufacturing stacked dynamic random access memory using reduced photomask steps was achieved. The invention utilizes two masking steps for forming the array of stacked capacitors and bit line contacts. One of the masking steps is used to concurrently form the bit line contact openings and to define the capacitor top electrode area for the stacked capacitors. After forming the array of field effect transistors by conventional means, an array of capacitor bottom electrodes is patterned from an N.sup.+ doped polysilicon layer using the first photoresist mask and plasma etching. An interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped second poly-silicon layer and insulating layer are deposited. The insulating layer and second polysilicon layer are patterned with a second photoresist mask and plasma etched to concurrently form the bit line contact openings and to define the capacitor top electrode plate. The sidewalls of the exposed second polysilicon layer in the bit line contact openings are then oxidized to prevent the top electrode plate from shorting to the bit lines which are then patterned from a polycide layer that extends over and in the bit line contact openings.

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patent: 5389566 (1995-02-01), Lage
patent: 5498562 (1996-03-01), Dennison et al.
patent: 5500544 (1996-03-01), Park et al.

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