Process for fabricating read-only memory cells

Details Process for fabricating read-only memory cells Process for fabricating read-only memory cells

1995-09-22

1997-05-27

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438130, 438586, 438587, H01L 21265, H01L 2170, H01L 2700, H01L 2144

Patent

active

056331878

ABSTRACT:
A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a gate oxide layer, a first polysilicon layer, and a first silicide layer are formed subsequently on the surface of a silicon substrate. The layers are patterned to form parallel strip-shaped configurations extending along a first direction on the surface of the silicon substrate. Next, impurities are implanted into the surface of the substrate in the areas between the strip-shaped configurations thereby constituting buried bit lines of the memory cells. Sidewall spacers are then formed on the sidewalls of the strip-shaped configurations. A second silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process, thereby improving the electrical conductivity of the buried bit lines. After that, the portions of the second silicide layer and the first polysilicon layer covering the coding region of the memory cells are removed. A thick insulating layer is then formed to cover the entire substrate surface. The surface of the thick insulating layer is then polished to an extent revealing the surface of the first polysilicon. Finally, a second polysilicon layer is formed on the substrate covering the surface of the thick insulating layer and the exposed first polysilicon layer. An etching procedure is then performed to form parallel strip-shaped word lines in the second polysilicon layer that extend in a second direction on the plane of the substrate, with the second direction substantially orthogonal to the first direction. Portions of the first polysilicon not covered by the word lines are also removed in the etching procedure.

REFERENCES:
patent: 4143390 (1979-03-01), Noguchi
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 5504030 (1996-04-01), Chung et al.

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