Method of making volatile memory cell with interface charge trap

Details Method of making volatile memory cell with interface charge trap Method of making volatile memory cell with interface charge trap

1995-06-07

1997-05-27

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438910, 438953, H01L 21266

Patent

active

056331789

ABSTRACT:
A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.

REFERENCES:
patent: Re31083 (1982-11-01), DeKeersmaecker et al.
patent: 3856587 (1974-12-01), Yamazaki et al.
patent: 4047974 (1977-09-01), Harari
patent: 4217601 (1980-08-01), DeKeersmaecker et al.
patent: 4868618 (1989-09-01), Kalnitsky et al.
European Search Report from European Patent Applications No. 93420474.4, filed Nov. 29, 1993.
Solid State Electronics, vol. 33, No. 5, May 1990, Oxford GB, pp. 523-530, A. Kalnitsky, et al., "Electric States At S1-S102 Interface Introduced by Implantation of S1 in Thermal S102".

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