Process for fabricating field effect transistor with a self-alig

Details Process for fabricating field effect transistor with a self-alig Process for fabricating field effect transistor with a self-alig

1998-04-30

2000-01-25

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438296, 438586, H01L 213205, H01L 214763

Patent

active

060178108

ABSTRACT:
Semiconductor devices are fabricated by providing a substrate having an insulating layer on the substrate, a conductive layer on the insulating layer and isolation regions through the conductive layer into the substrate insulating layer and forming a photo-resist layer on the isolating regions and on the conductive layer, forming an opening through the resist having a preselected shape at least over a portion of the conductive layer, partially etching some of the conductive layer through the opening selectively to the material of the device isolation region; removing the resist layer; depositing a conductive material on the etched conductive layer through the opening; planarizing the isolation regions, the conductive layer and the conductive material; etching the conductive-forming layer and the insulating layer except beneath the conductive material including exposing portions of the substrate for forming source/drain regions in the substrate.

REFERENCES:
patent: 5691215 (1997-11-01), Dai et al.
patent: 5904531 (1999-05-01), Liaw
patent: 5911111 (1999-06-01), Bohr et al.
patent: 5940707 (1999-08-01), Gardner et al.

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