Method of making a capacitor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438255, H01L 218242

Patent

active

057862508

ABSTRACT:
A method of the present invention forms a vertically oriented structure connected with a source/drain region through an open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad. A dry etching process is used to remove a segment of the conductive layer formed over the volume of insulating material upon the landing pad, after which the volume of insulating material upon the landing pad is removed. Remaining is a storage node made upon of a continuous layer of conductive material that lines the recess and the open space. A dielectric layer and a cell plate are in one embodiment formed over the continuous layer of conducting material so as to extend down into the open space, thus completing a container capacitor.

REFERENCES:
patent: 5082797 (1992-01-01), Chan et al.
patent: 5298792 (1994-03-01), Manning
patent: 5340774 (1994-08-01), Yen
patent: 5392189 (1995-02-01), Fazan
patent: 5401681 (1995-03-01), Dennison
patent: 5605857 (1997-02-01), Jost et al.

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