Memory device communication line control

Details Memory device communication line control Memory device communication line control

1997-02-14

1998-03-24

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Precharge

365149, G11G 700

Patent

active

057320365

ABSTRACT:
A memory device is described which equilibrates and precharges the input/output lines synchronously during a write cycle and asynchronously during a read cycle. During a read cycle, the timing of equilibration and precharge functions are decoupled from the clock signal and asynchronously initiate the equilibrate and precharge functions of the I/O lines in response to a latch signal. The invention initiates the equilibration and precharging of the I/O lines earlier in the access cycle thereby increasing memory access speed.

REFERENCES:
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patent: 4903238 (1990-02-01), Miyatake et al.
patent: 4996671 (1991-02-01), Suzuki et al.
patent: 5233560 (1993-08-01), Foss et al.
patent: 5495449 (1996-02-01), Park
patent: 5546338 (1996-08-01), Proebsting
"Micron 4 MEG X 4/2 MEG X 8 SDRAM", Micron Synchronous DRAM Data Book, Micron Technology, Inc., 1-44, (Rev. Feb. 1997).

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