Method for concurrently making thin-film-transistor (TFT) gate e

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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438154, 438621, 257903, H01L 2100, H01L 2184

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active

057312320

ABSTRACT:
A method is achieved for making TFT-load static random access memory (SRAM) cells where the thin film transistor (TFT) gate electrodes are made from an electrical conductor. At the same time, portions of the conductor between P and N doped polysilicon interconnections eliminate the P/N junction. Ohmic contacts are formed while avoiding additional processing steps. N-channel FET gate electrodes are formed from an N.sup.+ doped first polysilicon layer having a first insulating layer thereon. Second polySi interconnections are formed with a second insulating layer thereon. First contact openings are etched in the first and second insulating layers to the N.sup.+ doped FET gate electrodes, and a patterned conductor (TiN, TiSi.sub.2) forms the P-channel TFT gate electrodes and concurrently forms portions over and in the first contact openings. A TFT gate oxide is formed and second contact openings are etched over the first contact openings to the conductor. An N.sup.- doped third polySi layer is deposited, selectively doped P.sup.+ and patterned to form the TFT N.sup.- doped channel, the P.sup.+ doped source/drains, and the interconnection in the contact openings to the N-FET gate electrodes. The conductor at the interface between the P/N polySi forms essentially ohmic contacts, thereby eliminating the P/N junction and improving circuit performance.

REFERENCES:
patent: 5393682 (1995-02-01), Liu
patent: 5403762 (1995-04-01), Takemura
patent: 5468662 (1995-11-01), Havemann
patent: 5545584 (1996-08-01), Wuu et al.
patent: 5652174 (1997-07-01), Wuu et al.

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