Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-09-17
1999-07-13
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438595, H01L 21336
Patent
active
059239867
ABSTRACT:
A method of forming a wide top spacer (50 20S 40A) that prevents salicide bridging. The wide top spacer (50) consists of a first spacer (20S) and an upper spacer (40A) (half spacer). The upper spacer (40A) is formed by covering the first spacer with a sacrificial layer (30) and forming the upper spacer (40A) on a top portion of the first spacer. During a subsequent salicide process, the upper spacer (40A) prevents sputtered metal (60) from forming of an area (51) on the first spacer under the upper spacer (40A). This prevents shorting between the S/D (12) and the gate (18).
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Ackerman Stephen B.
Bowers Charles
Chen Jack
Saile George O.
Stoffel William J.
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