Static information storage and retrieval – Read/write circuit – Precharge
Patent
1997-02-26
1999-04-13
Zavabian, A.
Static information storage and retrieval
Read/write circuit
Precharge
36523008, G11C 700
Patent
active
058944427
ABSTRACT:
The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.
REFERENCES:
patent: Re35750 (1998-03-01), Casper
patent: 4969125 (1990-11-01), Ciraula
patent: 5475642 (1995-12-01), Taylor
patent: 5625598 (1997-04-01), Oba
patent: 5640363 (1997-06-01), Furutani et al.
Kabushiki Kaisha Toshiba
Zavabian A.
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