Method of making self-aligned stacked gate flush memory with hig

Details Method of making self-aligned stacked gate flush memory with hig Method of making self-aligned stacked gate flush memory with hig

1998-07-09

2000-10-10

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438259, 438266, 438267, 438296, 257315, 257316, H01L 21336

Patent

active

061301299

ABSTRACT:
An improved process for fabricating flash memory cells with high control-gate-to-floating-gate coupling ratio is disclosed. The flash memory cell contains: (a) a substrate; (b) at least a pair of spaced-apart floating gates on the substrate, each of the floating gate has a pair of poly sidewall spacers; (c) a field oxide layer (FOX) partially recessed into the substrate; (d) an oxide
itride/oxide (ONO) layer covering each of the floating gates; (e) a control gate covering the oxide
itride/oxide layer and the field oxide layer. The design of the flash memory cell allows the field oxide layer to be wedged between the pair of floating gates and below the poly sidewall spacers. The poly sidewall spacers substantially increases the overlapping area between the control gate and the floating gate, thus allowing the control-gate-to-floating-gate coupling ratio and the performance of the flash memory to be enhanced. Also, since the field oxide layer and the floating gates are self-aligned, high density flash memory can be made from this process. Furthermore, the distance between the floating gates can be shorter than that limited by the underlying photolithography technology.

REFERENCES:
patent: 5923974 (1999-07-01), Liang et al.

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