Method for simultaneously forming local interconnect with silici

Details Method for simultaneously forming local interconnect with silici Method for simultaneously forming local interconnect with silici

Filed on

1997-02-07

Date issued

1999-04-13

Examiner

Booth, Richard A.

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

438649, 438683, 117 9, H01L 21336

Type

Patent

Status

active

Patent number

058937412

Description

ABSTRACT:
A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a photoresist mask to map out where the local interconnection and source/drain are to be located. The final recited step is to deposit a thin metal layer to provide for the silicidation to complete the transistor. The silicon layer that is deposited has a thickness of 20 to 300 millimeters, and the thin metal layer is either cobalt or titanium having a thickness of 10 millimeters to 100 millimeters.

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Kotaki et al., "Novel Elevated Silicide Source/Drain (ESSOD) by Load-Lock LPCVD-Si and Advanced Silicidation Processing", IEDM, pp. 34.3.1-34.3.4, 1993.

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