Structure for folded architecture pillar memory cell

Details Structure for folded architecture pillar memory cell Structure for folded architecture pillar memory cell

1998-06-09

2000-09-05

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257333, 257332, 257301, 257329, 257328, H01L 2976, H01L 2994, H01L 3162, H01L 31113, H01L 31119

Patent

active

061147257

ABSTRACT:
A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

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