Stack capacitor DRAM cell having increased capacitor area

Details Stack capacitor DRAM cell having increased capacitor area Stack capacitor DRAM cell having increased capacitor area

1988-12-13

1995-01-03

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, 257756, H01L 2978, H01L 2992

Patent

active

053789083

ABSTRACT:
A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.

REFERENCES:
patent: 4635090 (1987-01-01), Tanaki et al.
patent: 4641166 (1987-02-01), Takemae et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4974040 (1990-11-01), Taguchi et al.

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