Method of fabricating a semiconductor memory device having a tre

Details Method of fabricating a semiconductor memory device having a tre Method of fabricating a semiconductor memory device having a tre

1998-03-31

2000-06-06

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438239, 438396, 438397, 438244, H01L 218242, H01L 2120

Patent

active

060717726

ABSTRACT:
A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer. The insulating material is wet-etched away, leaving the conductive segment attached to the truck-like layer as a branch-like conductive layer. A dielectric layer is formed over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer, and a further conductive layer is formed overlaying the dielectric layer to serve as an opposing electrode of the tree-type capacitor.

REFERENCES:
patent: 5739060 (1998-04-01), Chao
patent: 5863821 (1999-01-01), Chao
"Mini-Trenches in Polysilicon for Dram Storage Capacitance Enhancement", IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", International Electron Devices Meeting, pp. 592-595, Dec. 1988.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical papers, pp. 69-70.

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