Semiconductor memory device having a first source line arranged

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257315, 257396, 257748, 257754, 257756, 257758, 257765, 257774, 257775, 257776, H01L 2976, H01L 2994

Patent

active

061602973

ABSTRACT:
A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.

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S. Aritome, et al., "A 0.67um.sup.2 Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) for 3V-only 256Mbit Nand EEPROMs", 1994 IEEE, IEDM 94-61.

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