Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-05-14
1997-09-16
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
148DIG109, 148DIG163, 438286, H01L 218247
Patent
active
056680341
ABSTRACT:
High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices. A uni-sided lightly doped drain structure is created in n-channel enhancement and intrinsic high voltage devices only by an appropriately shaped mask to block the n+ source-drain implant over a previously implanted tip region disposed between the gate and drain, thereby minimizing hot-carrier effects in the drains. Metallization for the high voltage transistors is made over field oxide to the polysilicon control gates formed from the first polysilicon layer.
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Sery George E.
Smudski Jan A.
Intel Corporation
Trinh Michael
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