Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1994-06-30
1997-09-16
Wilczewski, Mary
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438558, H01L 21336
Patent
active
056680279
ABSTRACT:
A MOS transistor semiconductor device has a gate electrode portion with a spacer film, diffused regions diffused with dopants, and element-separating regions. After the formation of the gate on the substrate, a spacer oxide is formed adjacent to the gate. A polysilicon layer doped with the same dopants as the diffused regions is formed between the element-separating regions and the spacer film. The polysilicon layer is overlaps portions of the gate electrode and the element-separating regions that are close to the diffused regions. Thermal diffusion of the dopants from the polysilicon layer to the substrate is performed to further dope the diffused regions. After an insulation layer is formed over the polysilicon layer, connection holes are formed through the insulation layer to connect the polysilicon layer to metal interconnects. In this MOS transistor, the polysilicon layer provides holes that are larger in diameter than holes at the openings of the diffused regions that are part of the substrate surface. Therefore, the area on the silicon substrate surface occupied by diffused layers is reduced to permit semiconductor elements to be packed at a high density. The resistances of interconnects are also suppressed.
REFERENCES:
patent: 4041518 (1977-08-01), Shimizu et al.
patent: 4353085 (1982-10-01), Sakurai
patent: 4735916 (1988-04-01), Homma et al.
patent: 4822754 (1989-04-01), Lynch et al.
patent: 4826782 (1989-05-01), Sachitano et al.
patent: 4931845 (1990-06-01), Ema
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5113234 (1992-05-01), Furuta et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5314832 (1994-05-01), Deleonibus
patent: 5395787 (1995-03-01), Lee et al.
patent: 5547885 (1996-08-01), Ogoh
Wolf et al., Silicon Processing for the VLSI Era; vol. 1: Process Technology, Lattice Press, 1986, pp. 189-191, 320.
T.H. Ning, "Silicon-Gate MOSFET with Self-Aligned Buried Source and Drain Contacts", IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, pp. 5190-5193.
Nippon Steel Semiconductor Corporation
Wilczewski Mary
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