Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-11-12
2000-12-12
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438250, 438251, 438252, 438253, 438393, 438394, 438396, H01L 21336, H01L 218242
Patent
active
061598089
ABSTRACT:
A method of forming a dynamic random access memory cell such that the gate conductive layer, the bit line contact, the node contact, the bit line and the node contact plug are all formed using self-aligned processes. By employing the self-aligned method of forming DRAM cell, isolation structures are no longer etched in the process of forming the node contact opening. In addition, the aspect ratio of the node contact opening is reduced and processing window is thereby widened.
REFERENCES:
patent: 4378627 (1983-04-01), Jambotkar
patent: 5219777 (1993-06-01), Kang
patent: 5296400 (1994-03-01), Park et al.
patent: 5472897 (1995-12-01), Hsu et al.
patent: 5545579 (1996-08-01), Liang et al.
patent: 5956594 (1999-09-01), Yang et al.
patent: 6037216 (2000-03-01), Liu et al.
Kennedy Jennifer M.
Tsai Jey
United Microelectronics Corp.
United Semiconductor Corp.
Wu Charles C. H.
LandOfFree
Method of forming self-aligned DRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming self-aligned DRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming self-aligned DRAM cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-216210