Method of fabricating a flash memory with a planarized topograph

Details Method of fabricating a flash memory with a planarized topograph Method of fabricating a flash memory with a planarized topograph

1998-08-20

2000-12-12

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438592, 257315, 257324, H01L 21336

Patent

active

06159797&

ABSTRACT:
A method of fabricating a flash memory includes successive formation of a first polysilicon layer, a first dielectric layer and a hard material layer on a substrate with a tunnelling oxide layer. Then the hard material layer, the first dielectric layer and the first polysilicon layer are defined and the first polysilicon layer serves as a floating gate of the flash memory. After the step of definition, a source/drain region is formed on the substrate on the sides of the floating gate and an insulating spacer is also formed thereon. An inter-poly dielectric layer is then formed over the substrate and CMP is performed to etch back the inter-poly dielectric layer, exposing the surface of the hard material layer serving as a stop layer. Next, the hard material layer is removed and the first polysilicon layer is doped with impurities. A second dielectric layer is formed over the substrate and covers the surface of the first polysilicon layer. Subsequently, the second polysilicon layer is formed and defined to serve as a control gate of the flash memory.

REFERENCES:
patent: 5094967 (1992-03-01), Shinada et al.
patent: 5474947 (1995-12-01), Chang et al.
patent: 5566106 (1996-10-01), Bergemont
patent: 5912487 (1999-06-01), Hong
patent: 5981365 (1999-11-01), Cheek et al.
patent: 6063675 (2000-05-01), Rodder

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