Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1998-08-10
1999-11-02
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518909, G11C 1300
Patent
active
059782803
ABSTRACT:
A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.
REFERENCES:
patent: 5193076 (1993-03-01), Houston
patent: 5291447 (1994-03-01), Kodama et al.
patent: 5309395 (1994-05-01), Dickinson et al.
patent: 5325337 (1994-06-01), Buttar
patent: 5388075 (1995-02-01), Vinal
patent: 5394361 (1995-02-01), Dickinson
patent: 5473565 (1995-12-01), Kusakari
patent: 5473568 (1995-12-01), Okamura
patent: 5479374 (1995-12-01), Kobayashi et al.
patent: 5502681 (1996-03-01), Park
patent: 5508604 (1996-04-01), Keeth
patent: 5544101 (1996-08-01), Houston
patent: 5559752 (1996-09-01), Stephens, Jr. et al.
patent: 5596539 (1997-01-01), Passow et al.
patent: 5604705 (1997-02-01), Ackland et al.
patent: 5610862 (1997-03-01), Teel
patent: 5625595 (1997-04-01), Ikeda
patent: 5644773 (1997-07-01), Sawada
patent: 5659513 (1997-08-01), Hirose et al.
patent: 5661417 (1997-08-01), Kondoh
patent: 5661691 (1997-08-01), Lin
patent: 5717653 (1998-02-01), Suzuki
patent: 5724287 (1998-03-01), Takenaka
patent: 5729503 (1998-03-01), Manning
patent: 5742552 (1998-04-01), Greenberg
patent: 5745419 (1998-04-01), Brauch
patent: 5748544 (1998-05-01), Hashimoto
patent: 5751170 (1998-05-01), Pyeon
patent: 5752270 (1998-05-01), Wada
patent: 5754481 (1998-05-01), Yabe et al.
patent: 5757718 (1998-05-01), Suzuki
patent: 5761136 (1998-06-01), Park et al.
Hunt et al., Self-Timed Sense Amplifier Evaluation Scheme, Jun. 24, 1998, U.S.S.N. 09/103,960.
Jeffrey S. Hunt et al., U.S.S.N. 09/107,000 Method, Architecture and Circuit for Writing to and Reading from a Memory During a Single Cycle, filed Jun. 29, 1998.
Jeffrey S. Hunt et al. U.S.S.N. 09/106,806 Method, Architecture and Circuit for Writing to a Memory, filed Jun. 29, 1998.
Satish Saripella et al., U.S.S.N. 09/126,832 Wordline Synchronized Reference Voltage Generator, filed Jul. 31, 1998.
Jeffrey S. Hunt et al., U.S.S.N. 09/103,960 Self-Timed Sense Amplifier Evalution Scheme, filed Jun. 24, 1998.
Anumula Sudhaker Reddy
Hunt Jeffery Scott
Saripella Satish C.
Srikrishna Ajay
Cypress Semiconductor Corp.
Fears Terrell W.
Maiorana P.C. Christopher P.
LandOfFree
Method, architecture and circuit for reducing and/or eliminating does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, architecture and circuit for reducing and/or eliminating, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, architecture and circuit for reducing and/or eliminating will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2144731