Method of making enhancement-mode and depletion-mode IGFETs with

Details Method of making enhancement-mode and depletion-mode IGFETs with Method of making enhancement-mode and depletion-mode IGFETs with

1997-04-21

1999-11-02

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438549, 438275, H01L 218236

Patent

active

059769386

ABSTRACT:
A method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a first gate with a first thickness over the first device region, forming a second gate with a second thickness over the second device region, wherein the second thickness is substantially greater than the first thickness, implanting a dopant into the substrate and into the first and second gates to implant source and drain regions in the first device region and source and drain regions in the second device region, and transferring the dopant through the first gate into a first channel region in the first device region beneath the first gate without transferring essentially any of the dopant through the second gate into a second channel region in the second device region beneath the second gate, thereby providing depletion-mode doping in the first channel region while retaining enhancement-mode doping in the second channel region. The dopant can be implanted through the first gate into the first channel region. Alternatively, the dopant can be implanted into the first gate but not the first channel region and then diffused from the first gate into the first channel region. Advantageously, by employing different gate thicknesses, a single implant step can be used to provide lightly doped source/drain regions for enhancement and depletion-mode IGFETs as well as depletion-mode doping for channel regions of depletion-mode IGFETs (with thin gates) while retaining enhancement-mode doping for channel regions of enhancement-mode IGFETs (with thick gates).

REFERENCES:
patent: 3829888 (1974-08-01), Hashimoto et al.
patent: 4085498 (1978-04-01), Rideout
patent: 4329186 (1982-05-01), Kotecha et al.
patent: 4725871 (1988-02-01), Yamazaki
patent: 5149664 (1992-09-01), Shin et al.
patent: 5300443 (1994-04-01), Shimabukuro et al.
Silicon Processing for the VLSI Era--vol. 3: The Submicron MOSFET, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1995, pp. 554-555.

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