Method of fabricating an electrically erasable and programmable

Details Method of fabricating an electrically erasable and programmable Method of fabricating an electrically erasable and programmable

1998-09-08

1999-11-02

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438592, 438594, H01L 21336

Patent

active

059769351

ABSTRACT:
A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

REFERENCES:
patent: 4851361 (1989-07-01), Schumann et al.
patent: 5591658 (1997-01-01), Cacharelis
patent: 5637520 (1997-06-01), Cappelletti et al.
patent: 5679970 (1997-10-01), Hartmann
patent: 5714412 (1998-02-01), Liang et al.
patent: 5793081 (1998-08-01), Tomioka et al.

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