Semiconductor memory device having sub dummy bit line and sub du

Details Semiconductor memory device having sub dummy bit line and sub du Semiconductor memory device having sub dummy bit line and sub du

1997-10-31

1999-03-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

36523003, 36523006, G11C 702

Patent

active

058869395

ABSTRACT:
A semiconductor memory device accurately reads out data from a normal unit cell when a short bridge occurs between the normal unit cell and a dummy unit cell. A sub dummy bit line pair DBL/DBLB is interposed between a sub normal bit line and a sub word line driver region (or a strap region). A direct contact (DC) between the dummy unit cell and a sub dummy bit line is eliminated. A data storage capacitor of the dummy unit cell normally connected to a sub dummy bit line DBLB by way of a buried contact is also removed. Thus, operational errors caused by short bridges created between normal and during unit cells are eliminated.

REFERENCES:
patent: 5299165 (1994-03-01), Kimura et al.
patent: 5410509 (1995-04-01), Morita
patent: 5553027 (1996-09-01), Von Der Ropp
patent: 5652728 (1997-07-01), Hosotani et al.
patent: 5694369 (1997-12-01), Abe
patent: 5701269 (1997-12-01), Fujii

Affiliated with

Also associated with

Rating

Semiconductor memory device having sub dummy bit line and sub du does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having sub dummy bit line and sub du, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having sub dummy bit line and sub du will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2132939