Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1995-12-20
1997-11-25
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257697, 257773, 361772, 361791, H01L 2348, H01L 2352
Patent
active
056915691
ABSTRACT:
A contact pattern for an integrated circuit package. The package has a plurality of contacts that are soldered to corresponding pads of a printed circuit board. The contacts are arranged into a plurality of cell units. Each cell unit has a row of center contacts diagonally located between two rows of outer contacts. The diagonally located pins increase the density of the contact pattern. Each unit cell is separated by a space that allows routing traces to be routed therethrough. Routing traces may also be routed through the unit cells to increase the routing density of the package. The package provides a contact pattern that optimizes both the pin density and the routing traces.
REFERENCES:
patent: 4254445 (1981-03-01), Ho
patent: 4322778 (1982-03-01), Barbour et al.
patent: 4338621 (1982-07-01), Braun
patent: 4616406 (1986-10-01), Brown
patent: 4930002 (1990-05-01), Takenaka et al.
patent: 4942453 (1990-07-01), Ishida et al.
patent: 5061989 (1991-10-01), Yen et al.
patent: 5266826 (1993-11-01), Umeyama
patent: 5490040 (1996-02-01), Gavdenzi et al.
Intel Corporation
Ostrowski David
Thomas Tom
LandOfFree
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