Multilevel sequence of erase pulses for amorphous memory devices

Static information storage and retrieval – Systems using particular element – Amorphous

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357 2, G11C 700

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active

042285240

ABSTRACT:
The Write/Erase lifetime of amorphous memory devices are extended by applying an erase pulse sequence having a first plurality of reset voltage pulses having a maximum amplitude less than the maximum threshold of the device to produce first amplitude current pulses and a second plurality of reset voltage pulses having a maximum amplitude greater than the maximum threshold to produce second amplitude current pulses having an amplitude substantially less than said current pulses. Constant current sources apply the two current pulses when the device threshold is below the maximum voltage amplitude of the first reset voltage pulses and only the second amplitude current pulses when the device threshold exceeds the maximum voltage amplitude of the first reset voltage pulses.

REFERENCES:
patent: 3827033 (1974-07-01), Quilliam
patent: 3846767 (1974-11-01), Cohen
patent: 3875566 (1975-04-01), Helbers
patent: 3886577 (1975-05-01), Buckley
patent: 3922648 (1975-11-01), Buckley
Manhart et al., Automatic `try and verify` Circuit to Investigate the Reliability of Memory Switching in Amorphous Materials, Journal of Physics E: Scientific Instruments, 1975, vol. 8, pp. 317-321.

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