Memory with compensation for voltage, temperature, and processin

Details Memory with compensation for voltage, temperature, and processin Memory with compensation for voltage, temperature, and processin

1992-01-23

1994-04-12

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Signals

365211, 36518909, 307591, 307594, 3072961, G11C 1300

Patent

active

053031911

ABSTRACT:
A memory (30) includes input buffers (35, 38, 56), decoders (31, 32, 36), and a memory portion (34). The input buffers (35, 38, 56) include a delay circuit (82) which delays at least one transition of an input signal. The delay circuit (82) includes a compensation circuit (250) which compensates the delay circuit (82) for voltage, temperature, and processing variations. In one embodiment, the delay circuit (82) includes a CMOS inverter (102, 103) with an additional transistor (101) coupled between a source of an inverter transistor (102) and a corresponding power supply voltage. The compensation circuit (250) provides a bias voltage to bias a gate of the transistor (101) to determine the delay of the delay circuit (82). The compensation circuit (250) provides the bias voltage as that voltage which biases the transistor (101) to conduct a precision reference current.

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