Metallization structure and method for a semiconductor device

Details Metallization structure and method for a semiconductor device Metallization structure and method for a semiconductor device

1997-03-14

2000-09-26

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438299, 438621, 438643, 438653, 438633, 438670, H01L 213205

Patent

active

06124189&

ABSTRACT:
A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer. Subsequent steps include: removing the first insulating layer, thereby forming an unfilled region above the polysilicon layer; depositing a metal such as tungsten in the unfilled region and the contact hole; and polishing the deposited metal layer to planarize the upper surface of the metal with the upper surface of the second insulating layer.

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