Memory system using pipeline circuitry for improved speed

Details Memory system using pipeline circuitry for improved speed Memory system using pipeline circuitry for improved speed

1983-01-03

1986-06-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365220, G11C 1140, G11C 1300

Patent

active

045970610

ABSTRACT:
A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.

REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.

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