Method of fabricating EPROM memory by individually forming gate

Details Method of fabricating EPROM memory by individually forming gate Method of fabricating EPROM memory by individually forming gate

1996-02-20

1998-02-10

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438637, H01L 218247

Patent

active

057168741

ABSTRACT:
A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

REFERENCES:
patent: 4924437 (1990-05-01), Paterson et al.
patent: 5418741 (1995-05-01), Gill
patent: 5460991 (1995-10-01), Hong
patent: 5472892 (1995-12-01), Gwen et al.

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