Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-03-30
2000-06-13
Tran, Minh Loan
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257162, 257273, 257557, 257575, H01L 2976, H01L 27082
Patent
active
060752726
ABSTRACT:
An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The conserved surface space allows a higher density of structures per chip. The conductive sidewall members couple to the gate of the gated lateral bipolar transistor and, additionally, to a retrograded, more highly doped bottom layer. The improved structure provides for both metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction beneath the gate of the gated lateral bipolar transistor.
REFERENCES:
patent: 4450048 (1984-05-01), Gaulier
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4922315 (1990-05-01), Vu
patent: 4987089 (1991-01-01), Roberts
patent: 4996574 (1991-02-01), Shirasaki
patent: 5006909 (1991-04-01), Kosa
patent: 5023688 (1991-06-01), Ando et al.
patent: 5097381 (1992-03-01), Vo et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5250450 (1993-10-01), Lee et al.
patent: 5315143 (1994-05-01), Tsuji
patent: 5350934 (1994-09-01), Matsuda
patent: 5491356 (1996-02-01), Dennison et al.
patent: 5508544 (1996-04-01), Shah
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5541432 (1996-07-01), Tsuji
patent: 5554870 (1996-09-01), Fitch et al.
patent: 5581104 (1996-12-01), Lowrey et al.
patent: 5585998 (1996-12-01), Kotecki et al.
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5680345 (1997-10-01), Hsu et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5796143 (1998-08-01), Fulford, Jr. et al.
patent: 5796166 (1998-08-01), Agnello et al.
patent: 5892260 (1999-04-01), Okumura et al.
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conferece, Digest of Technical Papers, 286-287, (1997).
Horiguchi, et al., "Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSIs", IEEE Journal of Solid State Circuits, vol. 28, 1131-1135, (1993).
Jaeger, et al., "A High-speed Sensing Scheme for 1T Dynamic RAMs Utilizing the Clamped Bit-line Sense Amplifier", IEEE Journal of Solid State Circuits, vol. 27, 618-25, (1992).
Rabaey, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, NJ, 222-232, (1996).
Saito, M., et al., "Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996).
Seevinck, E., et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's", IEEE Journal of Solid-State Circuits, 26, 525-536, (Apr. 1991).
Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).
Tuinega, A Guide to Circuit Simulation and Analysis Using PSPICE, Prentice Hall, Englewood Cliffs, NJ, (1988).
Wong, et al., "A IV CMOS Digital Circuits with Double-Gate Driven MOSFET", IEEE Int. Solid State Circuits Conference, San Francisco, 292-93, (1997).
Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1986).
Chen, M.J., et al., "Optimizing the Match in Weakley Inverted MOSFET's by Gated lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chung I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30-Oct. 3, 1996).
Holman, W.T., et al., "A Compact Low Noise Operational Amplifier for a 1.2 MIcrometer Digital CMOS Technology", IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).
Huang, W.L., et al., "TFSOI Complementary BICMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).
Ko, et al., "High-gain Lateral Bipolar Action in a MOSFET Structure", IEEE Trans. on Electron Devices, vol. 38, No. 11, 2487-96, (Nov. 1991).
MacSweeney, D., et al., "Modelling of Lateral Bipolar Devices in a CMOS Process", IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, 27-30, (Sep. 1996).
Parke, S.A., et al., "A High-Performance Lateral Bipolar Transistor for Microprocessor-Based Smart Power Applications", IEEE Transactions on Electron Devices, 42, 564-570, (Mar. 1995).
Forbes Leonard
Noble Wendell P.
Micro)n Technology, Inc.
Tran Minh Loan
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