MOS memory

Details MOS memory MOS memory

1984-06-04

1986-04-08

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1140

Patent

active

045817189

ABSTRACT:
A pseudo-static type RAM composed of dynamic type memory cells is operated in response to the changes in external address signals. In the RAM of this type, the word line, with which the selection terminals of the memory cells are connected, are selected only for such a remarkably short time period as responds to the abnormally short period for which the external address signals are changed by address skews. If the selection period of the word line is short, the signal level to be rewritten in the memory cells is dropped so that the stored data are substantially broken. In order to prevent this breakage of the stored data, an address buffer is controlled. The reception of the external address signals by the address buffer is prohibited during the time period after the selection of the word line is started and before the rewriting operation of the data in the memory cells is ended.

REFERENCES:
patent: 4354232 (1982-10-01), Ryan

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