Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-06
1999-10-19
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438264, H01L 21316, H01L 218247
Patent
active
059703423
ABSTRACT:
The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate. A conductive layer is formed on the dielectric layer as control gate.
REFERENCES:
patent: 5352619 (1994-10-01), Hong
patent: 5427970 (1995-06-01), Hsue et al.
patent: 5460991 (1995-10-01), Hong
Shirai et al., "A 054um.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256Mbit Flash Memories", IEDM Tech. Dig., pp. 653-656, 1995.
Mao Daniel H.
Monin, Jr. Donald L.
Texas Instruments--Acer Incorporated
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