Method of making a plug transistor

Details Method of making a plug transistor Method of making a plug transistor

1998-01-07

1999-10-19

Fahmy, Wael M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438218, 438229, 438275, 438279, 438154, 257274, 257369, 257371, H01L 218238

Patent

active

059703318

ABSTRACT:
A method of making a plug transistor is disclosed. The method includes providing a semiconductor substrate with an active region of a first conductivity type, providing a doped layer of a second conductivity type in the active region, forming a dielectric layer over the active region, forming an opening in the dielectric layer, implanting a dopant of the first conductivity type through the opening into a portion of the doped layer beneath the opening thereby counterdoping the portion of the doped layer and splitting the doped layer into source and drain regions, forming a gate insulator on the active region and in the opening, and forming a gate on the gate insulator and in the opening and adjacent to the dielectric layer. Preferably, a single photoresist layer provides an etch mask for the dielectric layer and an implant mask for the dopant. It is also preferred that the gate is formed by depositing a blanket layer of gate material over the dielectric layer and into the opening and then polishing the gate material so that the gate is aligned with a top surface of the dielectric layer. In a CMOS process, the method includes forming the gate insulators and gates for the N-channel and P-channel devices separately and in sequence, and also includes forming the sources and drains for N-channel and P-channel devices before forming the gate for the P-channel device. In this manner, the N-channel and P-channel devices can have gate insulators and/or gates with different materials and/or thicknesses, and little or no boron penetration occurs, thereby providing excellent threshold voltage control.

REFERENCES:
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 5141891 (1992-08-01), Arima et al.
patent: 5166084 (1992-11-01), Pfiester
patent: 5175118 (1992-12-01), Yoneda
patent: 5231038 (1993-07-01), Yamaguchi et al.
patent: 5538913 (1996-07-01), Hong
patent: 5545579 (1996-08-01), Liang et al.
patent: 5567635 (1996-10-01), Acovic et al.
U.S. Patent application Ser. No. 08/739,593, filed Oct. 30, 1996, entitled Method of Forming Trench Transistor with Metal Spacers (As Amended), by Mark I. Gardner et al.
U.S. Patent application Ser. No. 08/739,595, filed Oct. 30, 1996, entitled Method of Forming a Trench Transistor with Insulative Spacers (As Amended), by Mark I. Gardner et al.
U.S. Patent application Ser. No.: 08/739,566, filed Oct. 30, 1996, entitled Method of Forming Trench Transistor and Isolation Trench (As Amended), by Mark I. Gardner et al.
U.S. Patent application Ser. No. 08/739,592, filed Oct. 30, 1996, entitled Trench Transistor with Localized Source/Drain Regions Implanted Through Voids in Trench, by Mark I. Gardner et al.
U.S. Patent application Ser. No. 08/739,596, filed Oct. 30, 1996, entitled Trench Transistor with Localized Source/Drain Regions Implanted Through Selectively Grown Oxide Layer, by Mark I. Gardner et al.
U.S. Patent application Ser. No. 08/739,597, filed Oct. 30, 1996, entitled Trench Transistor in Combination with Trench Array, by H. Jim Fulford, Jr. et al.
U.S. Patent application Ser. No. 08/739,567, filed Oct. 30, 1996, entitled Trench Transistor with Source Contact in Trench, by Mark I. Gardner et al.
U.S. Patent application Ser. No. 08/844,925, filed Apr. 21, 1997, entitled Method of Making Enhancement-Mode and Depletion-Mode IGFETS with Different Gate Thicknesses, by Mark I. Gardner.

Affiliated with

Also associated with

Rating

Method of making a plug transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a plug transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a plug transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2068292